The performance of logic has increased by two orders of magnitude over the past decade while the performance of memory has increased by less than a factor of two. Memory has become the critical bottleneck in most systems ranging from servers to routers to communications equipments. For example, the Internet revolution dramatically accelerated network performance requirements, but the technological limits of dynamic random access memory (DRAM) and static random access memory (SRAM) have created a bottleneck defined by the slow speed of DRAMs and the low density of SRAMs. System Designers have struggled for years to find a solution that successfully matches the density of DRAM with the high speed of SRAM. Recently, a new kind of memory cell based on a breakthrough Negative Differential Resistance based (NDR-based) SRAM cell has been developed. It provides the best of both worlds: SRAM speeds paired with DRAM density. The result is a memory cell that is four times faster than existing DRAMs and four times denser than state-of-the-art SRAMs. More detailed information about such memory cell can be found in U.S. Pat. No. 6,229,161.
Although the above mentioned NDR based SRAM memory cell provides better size/performance over conventional SRAM and DRAM, there is a need to further improve the size/performance of memory.